Demands for high-speed data processing and communication continue to push the electronics industry to develop faster and higher-functioning circuits while, at the same time, reducing power consumption. To various degrees, these demands have been realized in very large scale integration of circuits that operate at relatively low power supply voltages. Technologies such as telecommunications and networking, for example, continue to fuel research and design efforts that facilitate serial data rate capabilities on the order of tens or hundreds of gigabits per second and higher. In a typical application, the clock source provides the high-frequency signal that used to achieve these high serial data rate capabilities. In this manner, the high-speed clock source permits such circuitry to achieve its high-speed data-processing operation.
A challenge in such high-speed communication systems is that the systems can be expensive and difficult to upgrade. New semiconductor processes and circuits used to implement the high-speed communication systems are implemented with demands for improving cost and performance. However, it is difficult to meet these cost and performance demands in new designs when the newer designs require special and often outdated interface circuitry for connecting to components in the older systems. Thus, cost and performance are typically improved by providing creative approaches for retrofitting the newly designed components into the older systems. Where these creative approaches increase the overall speed of operation, additional cost and performance advantages can be realized.
As a specific example, newer processes and circuits would typically use power supply voltages that are much smaller that those used with old processes and circuits. To be backward compatible with older systems, the newer designs must be able to receive signals at a higher voltage than desired with the new process. While it may be possible to use on-chip AC-signal coupling to achieve a compatible interface between devices operating at different supply voltages, this approach assumes a requisite size for an on-chip capacitor that imposes an undesirable and/or intolerable lower limit on input frequencies.
Some communication standards also require that the high-speed data inputs be able to recover for long periods at a fixed value. The approach mentioned above cannot support this requirement without some modification since long term charge will build up on the AC-signal coupling capacitors and the time constant will be longer than required by many applications and standards.
Accordingly, an approach that addresses the aforementioned problems, as well as other related problems, is desirable.